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general description the max1290/max1292 low-power, 12-bit analog-to- digital converters (adcs) feature a successive-approxi- mation adc, automatic power-down, fast wake-up (2?), an on-chip clock, +2.5v internal reference, and a high-speed, byte-wide parallel interface. the devices operate with a single +5v analog supply and feature a v logic pin that allows them to interface directly with a +2.7v to +5.5v digital supply. power consumption is only 10mw (v dd = v logic ) at a 400ksps max sampling rate. two software-selectable power-down modes enable the max1290/max1292 to be shut down between conversions; accessing the par- allel interface returns them to normal operation. powering down between conversions can cut supply current to under 10? at reduced sampling rates. both devices offer software-configurable analog inputs for unipolar/bipolar and single-ended/pseudo-differen- tial operation. in single-ended mode, the max1290 has eight input channels and the max1292 has four input channels (four and two input channels, respectively, when in pseudo-differential mode). excellent dynamic performance and low power, com- bined with ease of use and small package size, make these converters ideal for battery-powered and data- acquisition applications or for other circuits with demand- ing power consumption and space requirements. the max1290/max1292 tri-states int when cs goes high. refer to max1262/max1264 if tri-stating int is not desired. the max1290 is available in a 28-pin qsop package, while the max1292 comes in a 24-pin qsop. for pin- compatible +3v, 12-bit versions, refer to the max1291/ max1293 data sheet. applications industrial control systems data logging energy management patient monitoring data-acquisition systems touchscreens features 12-bit resolution, 0.5 lsb linearity +5v single-supply operation user-adjustable logic level (+2.7v to +5.5v) internal +2.5v reference software-configurable analog input multiplexer 8-channel single-ended/ 4-channel pseudo-differential (max1290) 4-channel single-ended/ 2-channel pseudo-differential (max1292) software-configurable unipolar/bipolar analog inputs low current: 2.5ma (400ksps) 1.0ma (100ksps) 400a (10ksps) 2a (shutdown) internal 6mhz full-power bandwidth track/hold byte-wide parallel (8 + 4) interface small footprint: 28-pin qsop (max1290) 24-pin qsop (max1292) max1290/max1292 400ksps, +5v, 8-/4-channel, 12-bit adcs with +2.5v reference and parallel interface ________________________________________________________________ maxim integrated products 1 19-1531; rev 3; 12/02 part max1290 acei 0? to +70? temp range pin-package 28 qsop ordering information pin configurations 0.5 inl (lsb) max1290bcei 0? to +70? ? 28 qsop max1290beei max1290aeei -40? to +85? ? -40? to +85? ?.5 28 qsop 28 qsop ordering information continued at end of data sheet. typical operating circuits appear at end of data sheet. 24 23 22 21 20 19 18 17 16 15 14 13 1 2 3 4 5 6 7 8 9 10 11 12 v logic v dd ref refadj gnd com ch0 ch1 ch2 ch3 cs clk wr rd int d0/d8 d1/d9 d2/d10 d3/d11 d4 d5 d6 d7 hben qsop max1292 top view pin configurations continued at end of data sheet. evaluation kit available for pricing, delivery, and ordering information, please contact maxim/dallas direct! at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com.
max1290/max1292 400ksps, +5v, 8-/4-channel, 12-bit adcs with +2.5v reference and parallel inter face 2 _______________________________________________________________________________________ absolute maximum ratings electrical characteristics (v dd = v logic = +5v ?0%, com = gnd, refadj = v dd , v ref = +2.5v, 4.7? capacitor at ref pin, f clk = 7.6mhz (50% duty cycle), t a = t min to t max , unless otherwise noted. typical values are at t a = +25?.) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. external acquisition or external clock mode internal acquisition/internal clock mode max129_a external acquisition/internal clock mode external clock mode -3db rolloff sinad > 68db f in = 175khz, v in = 2.5v p-p (note 4) f in1 = 49khz, f in2 = 52khz max129_b no missing codes over temperature conditions ns 25 aperture delay ns 400 t acq t/h acquisition time ? 3.2 3.6 4 2.5 3.0 3.5 2.1 t conv conversion time (note 5) mhz 6 full-power bandwidth khz 350 full-linear bandwidth db -78 channel-to-channel crosstalk db 76 imd intermodulation distortion db 80 sfdr spurious-free dynamic range db -80 total harmonic distortion (including 5th-order harmonic) thd ?.5 inl relative accuracy (note 2) bits 12 res resolution db 67 70 sinad signal-to-noise plus distortion lsb ?.2 channel-to-channel offset matching ppm/? ? gain temperature coefficient lsb ? lsb ? dnl differential nonlinearity lsb ? offset error lsb ? gain error (note 3) units min typ max symbol parameter internal acquisition/internal clock mode external acquisition or external clock mode <200 ps <50 aperture jitter mhz 0.1 7.6 f clk external clock frequency % 30 70 duty cycle dc accuracy (note 1) dynamic specifications (f in (sine wave) = 50khz, v in = 2.5v p-p , 400ksps, external f clk = 7.6mhz, bipolar input mode) conversion rate v dd to gnd ..............................................................-0.3v to +6v v logic to gnd.........................................................-0.3v to +6v ch0?h7, com to gnd ............................-0.3v to (v dd + 0.3v) ref, refadj to gnd.................................-0.3v to (v dd + 0.3v) digital inputs to gnd ...............................................-0.3v to +6v digital outputs (d0?11, int ) to gnd ........................................... -0.3v to (v logic + 0.3v) continuous power dissipation (t a = +70?) 24-pin qsop (derate 9.5mw/? above +70?).........762mw 28-pin qsop (derate 8.00mw/? above +70?).......667mw operating temperature ranges max1290_c_ _/max1292_c_ _ ....................... 0? to +70? max1290_e_ _/max1292_e_ _ .....................-40? to +85? storage temperature range .............................-65? to +150? lead temperature (soldering, 10s) .................................+300?
v max1290/max1292 400ksps, +5v, 8-/4-channel, 12-bit adcs with +2.5v reference and parallel inter face _______________________________________________________________________________________ 3 electrical characteristics (continued) (v dd = v logic = +5v ?0%, com = gnd, refadj = v dd , v ref = +2.5v, 4.7? capacitor at ref pin, f clk = 7.6mhz (50% duty cycle), t a = t min to t max , unless otherwise noted. typical values are at t a = +25?.) conditions units min typ max symbol parameter 0 to 0.5ma output load to power down the internal reference for small adjustments on/off-leakage current, v in = 0 or v dd unipolar, v com = 0 v 1.0 v dd + 50mv v ref ref input voltage range ? 4.7 10 capacitive bypass at ref ? 0.01 1 capacitive bypass at refadj mv/ma 0.2 load regulation (note 7) v v dd - 1 refadj high threshold mv ?00 refadj input range ?0 ppm/? tc ref ref temperature coefficient ma 15 ref short-circuit current v 2.49 2.5 2.51 ref output voltage pf 12 c in input capacitance ? ?.01 ? multiplexer leakage current v analog input voltage range single ended and differential (note 6) 0v ref v in cs = v dd i source = 1ma i sink = 1.6ma v in = 0 or v dd v logic = 4.5v ? ?.1 ? i leakage three-state leakage current v v logic - 0.5 v oh output voltage high v 0.4 v ol output voltage low pf 15 c in input capacitance ? ?.1 ? i in input leakage current mv 200 v hys input hysteresis v 0.8 v il input voltage low v 4.0 cs = v dd pf 15 c out three-state output capacitance bipolar, v com = v ref / 2 -v ref /2 +v ref /2 v logic = 2.7v 2.0 v ih input voltage high v ref = 2.5v, f sample = 400ksps 200 300 shutdown mode ? 2 i ref shutdown ref input current analog inputs internal reference external reference at ref digital inputs and outputs
operating mode, max1290/max1292 400ksps, +5v, 8-/4-channel, 12-bit adcs with +2.5v reference and parallel inter face 4 _______________________________________________________________________________________ timing characteristics (v dd = v logic = +5v ?0%, com = gnd, refadj = v dd , v ref = +2.5v, 4.7? capacitor at ref pin, f clk = 7.6mhz (50% duty cycle), t a = t min to t max , unless otherwise noted. typical values are at t a = +25?.) conditions units min typ max symbol parameter standby mode operating mode, f sample = 400ksps 1.0 1.2 ma 2.5 2.9 2.9 3.4 i dd positive supply current v 4.5 5.5 v dd analog supply voltage 200 electrical characteristics (continued) (v dd = v logic = +5v ?0%, com = gnd, refadj = v dd , v ref = +2.5v, 4.7? capacitor at ref pin, f clk = 7.6mhz (50% duty cycle), t a = t min to t max , unless otherwise noted. typical values are at t a = +25?.) v logic current i logic c l = 20pf 210 ? power-supply rejection psr v dd = +5v ?0%, full-scale input ?.3 ?.9 mv f sample = 400ksps nonconverting v 2.7 v dd + 0.3 v logic digital supply voltage wr to clk fall setup time t cws 40 ns ns clk pulse width high ns clk period t ch 40 t cp 132 clk pulse width low t cl 40 ns data valid to wr rise time t ds 40 ns wr rise to data valid hold time t dh 0 ns clk fall to wr hold time t cwh 40 ns cs to clk or wr setup time t csws 60 ns clk or wr to cs hold time t cswh 0 ns cs pulse width t cs 100 ns wr pulse width (note 8) t wr 60 ns parameter symbol min typ max units conditions shutdown mode 210 0.5 0.8 power requirements ? external reference internal reference external reference internal reference
max1290/max1292 400ksps, +5v, 8-/4-channel, 12-bit adcs with +2.5v reference and parallel inter face _______________________________________________________________________________________ 5 note 1: tested at v dd = +5v, com = gnd, = 0, unipolar single-ended input mode. note 2: relative accuracy is the deviation of the analog value at any code from its theoretical value after offset and gain errors have been removed. note 3: offset nulled. note 4: on channel is grounded; sine wave applied to off channels. note 5: conversion time is defined as the number of clock cycles times the clock period; clock has 50% duty cycle. note 6: input voltage range referenced to negative input. the absolute range for the analog inputs is from gnd to v dd . note 7: external load should not change during conversion for specified accuracy. note 8: when bit 5 is set low for internal acquisition, wr must not return low until after the first falling clock edge of the conversion. timing characteristics (continued) (v dd = v logic = +5v ?0%, com = gnd, refadj = v dd , v ref = +2.5v, 4.7? capacitor at ref pin, f clk = 7.6mhz (50% duty cycle), t a = t min to t max , unless otherwise noted. typical values are at t a = +25?.) 3k ? 3k ? dout dout v logic a) high-z to v oh and v ol to v oh b) high-z to v ol and v oh to v ol c load 20pf c load 20pf figure 1. load circuits for enable/disable times t tr 10 40 ns c load = 20pf, figure 1 rd rise to output disable rd fall to output data valid t do 10 50 ns rd fall to int high delay t int1 50 ns cs fall to output data valid t do2 100 ns c load = 20pf, figure 1 c load = 20pf, figure 1 c load = 20pf, figure 1 t tc 10 60 ns c load = 20pf, figure 1 parameter symbol min typ max units conditions cs rise to output disable hben rise to output data valid t do1 10 50 ns c load = 20pf, figure 1 hben fall to output data valid t do1 10 80 ns c load = 20pf, figure 1
max1290/max1292 400ksps, +5v, 8-/4-channel, 12-bit adcs with +2.5v reference and parallel inter face 6 _______________________________________________________________________________________ typical operating characteristics (v dd = v logic = +5v, v ref = +2.500v, f clk = 7.6mhz, c l = 20pf, t a = +25?, unless otherwise noted.) -0.5 -0.2 -0.3 -0.4 -0.1 0 0.1 0.2 0.3 0.4 0.5 0 2000 1000 3000 4000 5000 integral nonlinearity vs. digital output code max1290/2 toc01 digital output code inl (lsb) -0.5 -0.2 -0.3 -0.4 -0.1 0 0.1 0.2 0.3 0.4 0.5 0 2000 1000 3000 4000 5000 differential nonlinearity vs. digital output code max1290/2 toc02 digital output code dnl (lsb) 0.1 10k 10 1 100 1k 100k 1000k supply current vs. sample frequency max1290/2 toc03 f sample (hz) i dd ( a) 1 10 100 1k 10k with internal reference with external reference 1.8 1.9 2.0 2.1 2.2 supply current vs. supply voltage max1290/2 toc04 v dd (v) i dd (ma) 4.50 5.00 4.75 5.25 5.50 r l = code = 101010100000 1.7 1.9 1.8 2.1 2.0 2.2 2.3 -40 10 -15 35 60 85 supply current vs. temperature max1290/2 toc05 temperature (?) i dd (ma) r l = code = 101010100000 930 950 940 970 960 980 990 4.50 5.00 4.75 5.25 5.50 standby current vs. supply voltage max1290/2 toc06 v dd (v) standby i dd ( a) 930 950 940 970 960 980 990 -40 10 -15 35 60 85 standby current vs. temperature max1290/2 toc07 temperature ( c) standby i dd ( a) 1.0 1.5 2.0 2.5 3.0 power-down current vs. supply voltage max1290/2 toc08 v dd (v) power-down i dd ( a) 4.50 5.00 4.75 5.25 5.50 1.8 2.0 1.9 2.1 2.2 -40 10 -15 35 60 85 power-down current vs. temperature max1290/2 toc09 temperature ( c) power-down i dd ( a)
max1290/max1292 400ksps, +5v, 8-/4-channel, 12-bit adcs with +2.5v reference and parallel inter face _______________________________________________________________________________________ 7 2.48 2.49 2.51 2.50 2.52 2.53 internal reference voltage vs. supply voltage max1290/2 toc10 v dd (v) v ref (v) 4.50 5.00 4.75 5.25 5.50 2.48 2.49 2.51 2.50 2.52 2.53 -40 10 -15 35 60 85 internal reference voltage vs. temperature max1290/2 toc 11 temperature ( c) v ref (v) -1.0 0 -0.5 0.5 1.0 offset error vs. supply voltage max1290/2 toc12 v dd (v) offset error (lsb) 4.50 5.00 4.75 5.25 5.50 -2 -1 0 1 2 offset error vs. temperature max1290/2 toc13 temperature ( c) offset error (lsb) -40 35 60 -15 10 85 -2 0 -1 1 2 gain error vs. supply voltage max1290/2 toc14 v dd (v) gain error (lsb) 4.50 5.00 4.75 5.25 5.50 0 0.5 1.0 1.5 2.0 gain error vs. temperature max1290/2 toc15 temperature ( c) gain error (lsb) -40 35 60 -15 10 85 50 150 100 200 250 logic supply current vs. supply voltage max1290/2 toc16 v dd (v) i logic ( a) 4.50 5.00 4.75 5.25 5.50 typical operating characteristics (continued) (v dd = v logic = +5v, v ref = +2.500v, f clk = 7.6mhz, c l = 20pf, t a = +25?, unless otherwise noted.) 0 50 150 100 200 250 -40 10 -15 35 60 85 logic supply current vs. temperature max1290/2 toc 17 temperature ( c) i logic ( a) -140 -120 -100 -80 -60 -40 -20 0 20 0 400 200 600 800 1000 1200 fft plot max1290/2 toc18 frequency (khz) amplitude (db) v dd = 5v f in = 50khz f sample = 400ksps
max1290/max1292 400ksps, +5v, 8-/4-channel, 12-bit adcs with +2.5v reference and parallel inter face 8 _______________________________________________________________________________________ pin description name function 1 hben high byte enable. used to multiplex the 12-bit conversion result. 1: four msbs are multiplexed on the data bus. 0: eight lsbs are available on the data bus. pin 2 d7 three-state digital i/o line (d7) 3 d6 three-state digital i/o line (d6) 4 d5 three-state digital i/o line (d5) 5 d4 three-state digital i/o line (d4) 6 d3/d11 three-state digital i/o line (d3, hben = 0; d11, hben = 1) 7 d2/d10 three-state digital i/o line (d2, hben = 0; d10, hben = 1) 8 d1/d9 three-state digital i/o line (d1, hben = 0; d9, hben = 1) 9 d0/d8 three-state digital i/o line (d0, hben = 0; d8, hben = 1) 10 int int goes low when the conversion is complete and the output data is ready. 11 rd active-low read select. if cs is low, a falling edge on rd enables the read operation on the data bus. 12 wr active-low write select. when cs is low in internal acquisition mode, a rising edge on wr latches in configuration data and starts an acquisition plus a conversion cycle. when cs is low in external acquisition mode, the first rising edge on wr ends acquisition and starts a conversion. 13 clk clock input. in external clock mode, drive clk with a ttl/cmos-compatible clock. in internal clock mode, connect this pin to either v dd or gnd. 14 cs active-low chip select. when cs is high, digital outputs ( int , d7?0) are high impedance. 15 ch7 analog input channel 7 16 ch6 analog input channel 6 17 ch5 analog input channel 5 18 ch4 analog input channel 4 19 ch3 analog input channel 3 20 ch2 analog input channel 2 21 ch1 analog input channel 1 22 ch0 analog input channel 0 23 com ground reference for analog inputs. sets zero-code voltage in single-ended mode and must be stable to ?.5 lsb during conversion. 24 gnd analog and digital ground 25 refadj bandgap reference output/bandgap reference buffer input. bypass to gnd with a 0.01? capacitor. when using an external reference, connect refadj to v dd to disable the internal bandgap reference. 26 ref bandgap reference buffer output/external reference input. add a 4.7? capacitor to gnd when using the internal reference. 27 v dd analog +5v power supply. bypass with a 0.1? capacitor to gnd. 28 v logic digital power supply. v logic powers the digital outputs of the data converter and can range from +2.7v to v dd + 300mv. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 max1290 max1292
max1290/max1292 400ksps, +5v, 8-/4-channel, 12-bit adcs with +2.5v reference and parallel inter face _______________________________________________________________________________________ 9 _______________detailed description converter operation the max1290/max1292 adcs use a successive- approximation (sar) conversion technique and an input track-and-hold (t/h) stage to convert an analog input signal to a 12-bit digital output. their parallel (8 + 4) out- put format provides an easy interface to standard micro- processors (?s). figure 2 shows the simplified internal architecture of the max1290/max1292. single-ended and pseudo-differential operation the sampling architecture of the adc? analog com- parator is illustrated in the equivalent input circuits in figures 3a and 3b. in single-ended mode, in+ is inter- nally switched to channels ch0?h7 for the max1290 (figure 3a) and to ch0?h3 for the max1292 (figure 3b), while in- is switched to com (table 3). in differen- tial mode, in+ and in- are selected from analog input pairs (table 4). in differential mode, in- and in+ are internally switched to either of the analog inputs. this configuration is pseudo- differential in that only the signal at in+ is sampled. the return side (in-) must remain stable within ?.5 lsb (?.1 lsb for best performance) with respect to gnd during a conversion. to accomplish this, connect a 0.1? capacitor from in- (the selected input) to gnd. during the acquisition interval, the channel selected as the positive input (in+) charges capacitor c hold . at the end of the acquisition interval, the t/h switch opens, retaining charge on c hold as a sample of the signal at in+. the conversion interval begins with the input multiplex- er switching c hold from the positive input (in+) to the negative input (in-). this unbalances node zero at the comparator? positive input. the capacitive digital-to- analog converter (dac) adjusts during the remainder of the conversion cycle to restore node zero to 0v within the limits of 12-bit resolution. this action is equivalent to transferring a 12pf [(v in+ ) - (v in- )] charge from c hold to the binary-weighted capacitive dac, which in turn forms a digital representation of the analog input signal. t/h three-state, bidirectional i/o interface 12 17k ? 8 8 4 8 4 8 successive- approximation register mux ( ) are for max1290 only. charge redistribution 12-bit dac clock analog input multiplexer control logic & latches ref refadj 1.22v reference d0 d7 8-bit data bus (ch5) (ch4) ch3 ch2 ch1 ch0 com clk cs wr rd int v dd hben gnd v logic max1290 max1292 a v = 2.05 comp (ch7) (ch6) figure 2. simplified functional diagram of 8-/4-channel max1290/max1292
analog input protection internal protection diodes, which clamp the analog input to v dd and gnd, allow each input channel to swing within (gnd - 300mv) to (v dd + 300mv) without damage. however, for accurate conversions near full scale, both inputs must not exceed (v dd + 50mv) or be less than (gnd - 50mv). if an off-channel analog input voltage exceeds the sup- plies by more than 50mv, limit the forward-bias input current to 4ma. track/hold the max1290/max1292 t/h stage enters its tracking mode on the rising edge of wr . in external acquisition mode, the part enters its hold mode on the next rising edge of wr . in internal acquisition mode, the part enters its hold mode on the fourth falling edge of clock after writing the control byte. note that, in internal clock mode, this is approximately 1? after writing the control byte. in single-ended operation, in- is connected to com and the converter samples the positive ??input. in pseudo-differential operation, in- connects to the nega- tive input ??and the difference of | (in+) - (in-) | is sam- pled. at the beginning of the next conversion, the positive input connects back to in+ and c hold charges to the input signal. the time required for the t/h stage to acquire an input signal depends on how quickly its input capacitance is charged. if the input signal? source impedance is high, the acquisition time lengthens and more time must be allowed between conversions. the acquisition time, t acq , is the maximum time the device takes to acquire the signal and is also the minimum time required for the signal to be acquired. calculate this with the following equation: t acq = 9 (r s + r in )c in where r s is the source impedance of the input signal, r in (800 ? ) is the input resistance, and c in (12pf) is the input capacitance of the adc. source impedances below 3k ? have no significant impact on the max1290/ max1292? ac performance. higher source impedances can be used if a 0.01? capacitor is connected to the individual analog inputs. along with the input impedance, this capacitor forms an rc filter, limiting the adc? signal bandwidth. input bandwidth the max1290/max1292 t/h stage offers a 350khz full- linear and a 6mhz full-power bandwidth that make it possible to digitize high-speed transients and measure periodic signals with bandwidths exceeding the adc? sampling rate by using undersampling techniques. to avoid aliasing high-frequency signals into the frequen- cy band of interest, anti-alias filtering is recommended. starting a conversion initiate a conversion by writing a control byte that selects the multiplexer channel and configures the max1290/max1292 for either unipolar or bipolar opera- tion. a write pulse ( wr + cs ) can either start an acqui- sition interval or initiate a combined acquisition plus max1290/max1292 400ksps, +5v, 8-/4-channel, 12-bit adcs with +2.5v reference and parallel inter face 10 ______________________________________________________________________________________ ch0 ch2 ch1 ch3 ch4 ch6 ch7 ch5 com c switch track t/h switch r in 800 ? c hold hold 12-bit capacitive dac ref zero comparator + 12pf single-ended mode: in+ = ch0 ch7, in- = com pseudo-differential mode: in+ and in- selected from pairs of ch0/ch1, ch2/ch3, ch4/ch5, and ch6/ch7 at the sampling instant, the mux input switches from the selected in+ channel to the selected in- channel. input mux figure 3a. max1290 simplified input structure ch0 ch1 ch2 ch3 com c switch track t/h switch r in 800 ? c hold hold 12-bit capacitive dac ref zero comparator + 12pf single-ended mode: in+ = ch0 ch3, in- = com pseudo-differential mode: in+ and in- selected from pairs of ch0/ch1 and ch2/ch3 at the sampling instant, the mux input switches from the selected in+ channel to the selected in- channel. input mux figure 3b. max1292 simplified input structure
max1290/max1292 400ksps, +5v, 8-/4-channel, 12-bit adcs with +2.5v reference and parallel inter face ______________________________________________________________________________________ 11 table 1. control byte functional description name function d4 0 sgl /dif sgl /dif = 0: pseudo-differential analog input mode sgl /dif = 1: single-ended analog input mode in single-ended mode, input signals are referred to com. in pseudo-differential mode, the voltage difference between two channels is measured (tables 2, 3). 1 0 d3 uni /bip standby power-down mode. clock mode is unaffected. 0 1 1 uni/ bip = 0: bipolar mode uni/ bip = 1: unipolar mode in unipolar mode, an analog input signal from 0 to v ref can be converted; in bipolar mode, the signal can range from -v ref /2 to +v ref /2. d2, d1, d0 normal operation mode. external clock mode is selected. 1 a2, a1, a0 address bits a2, a1, a0 select which of the 8/4 (max1290/max1292) channels is to be converted (tables 3, 4). normal operation mode. internal clock mode is selected. bit pd1, pd0 0 d7, d6 pd1 and pd0 select the various clock and power-down modes. full power-down mode. clock mode is unaffected. d5 acqmod acqmod = 0: internal acquisition mode acqmod = 1: external acquisition mode conversion. the sampling interval occurs at the end of the acquisition interval. the acqmod (acquisition mode) bit in the input control byte (table 1) offers two options for acquiring the signal: an internal and an external acquisition. the conversion period lasts for 13 clock cycles in either the internal or external clock or acquisition mode. writing a new control byte during a conversion cycle aborts the conversion and starts a new acquisition interval. internal acquisition select internal acquisition by writing the control byte with the acqmod bit cleared (acqmod = 0). this causes the write pulse to initiate an acquisition interval whose duration is internally timed. conversion starts when this acquisition interval (three external clock cycles or approximately 1? in internal clock mode) ends (figure 4). note that, when the internal acquisition is combined with the internal clock, the aperture jitter can be as high as 200ps. internal clock users wishing to achieve the 50ps jitter specification should always use external acquisition mode. external acquisition use external acquisition mode for precise control of the sampling aperture and/or dependent control of acquisi- tion and conversion times. the user controls acquisition and start-of-conversion with two separate write pulses. the first pulse, written with acqmod = 1, starts an acquisition interval of indeterminate length. the second write pulse, written with acqmod = 0 (all other bits in the control byte are unchanged), terminates acquisition and starts conversion on wr rising edge (figure 5). the address bits for the input multiplexer must have the same values on the first and second write pulses. power-down mode bits (pd0, pd1) can assume new values on the second write pulse (see the power-down modes section). changing other bits in the control byte corrupts the conversion. reading a conversion a standard interrupt signal, int , is provided to allow the max1290/max1292 to flag the microprocessor when the conversion has ended and a valid result is avail- able. int goes low when the conversion is complete and the output data is ready (figures 4 and 5). int returns high on the first read cycle or if a new control byte is written. selecting clock mode the max1290/max1292 operate with an internal or external clock. control bits d6 and d7 select either internal or external clock mode. the part retains the last-requested clock mode if a power-down mode is selected in the current input word. for both internal and external clock mode, internal or external acquisition
max1290/max1292 400ksps, +5v, 8-/4-channel, 12-bit adcs with +2.5v reference and parallel inter face 12 ______________________________________________________________________________________ t cs t csws t wr t conv t dh t acq t ds t int1 t d0 t d01 t tr high-z high-z high-z high-z cs wr d7 d0 int rd hben dout acqmod = "0" high/low byte valid high/low byte valid control byte t cswh figure 4. conversion timing using internal acquisition mode t cs t wr t acq t conv t dh t ds t int1 t d0 t d01 t tr t cshw t csws acqmod = "1" cs wr d7 d0 int rd hben dout acqmod = "0" high/low byte valid high/low byte valid control byte control byte high-z high-z high-z t dh high-z figure 5. conversion timing using external acquisition mode
can be used. at power-up, the max1290/max1292 enter the default external clock mode. internal clock mode select internal clock mode to release the ? from the burden of running the sar conversion clock. to select this mode, bit d7 of the control byte must be set to 1 and bit d6 must be set to 0; the internal clock frequency is then selected, resulting in a 3.6? conversion time. when using the internal clock mode, connect the clk pin either high or low to prevent the pin from floating. external clock mode to select the external clock mode, bits d6 and d7 of the control byte must be set to 1. figure 6a shows the clock and wr timing relationship for internal and exter- nal (figure 6b) acquisition modes with an external clock. proper operation requires a 100khz to 7.6mhz clock frequency with 30% to 70% duty cycle. operating the max1290/max1292 with clock frequencies lower than 100khz is not recommended, because it causes a voltage droop across the hold capacitor in the t/h stage that results in degraded performance. max1290/max1292 400ksps, +5v, 8-/4-channel, 12-bit adcs with +2.5v reference and parallel inter face ______________________________________________________________________________________ 13 wr clk clk wr wr goes high when clk is high. wr goes high when clk is low. t cws t ch t cl t cp t cwh acquisition starts acquisition starts conversion starts conversion starts acquisition ends acquisition ends acqmod = "0" acqmod = "0" figure 6a. external clock and wr timing (internal acquisition mode) wr clk clk wr wr goes high when clk is high. wr goes high when clk is low. t dh t dh t cwh t cws acquisition starts acquisition starts conversion starts conversion starts acquisition ends acquisition ends acqmod = "1" acqmod = "1" acqmod = "0" acqmod = "0" figure 6b. external clock and wr timing (external acquisition mode)
max1290/max1292 digital interface input (control byte) and output data are multiplexed on a three-state parallel interface. this parallel interface (i/o) can easily be interfaced with standard ?s. the signals cs , wr , and rd control the write and read operations. cs represents the chip-select signal, which enables a ? to address the max1290/max1292 as an i/o port. when high, cs disables the clk, wr , and rd inputs and forces the interface into a high-impedance (high-z) state. input format the control byte is latched into the device on pins d7 d0 during a write command. table 2 shows the control byte format. output format the output format for the max1290/max1292 is binary in unipolar mode and two? complement in bipolar mode. when reading the output data, cs and rd must be low. when hben = 0, the lower 8 bits are read. with hben = 1, the upper 4 bits are available and the output data bits d7?4 are set either low in unipolar mode or to the value of the msb in bipolar mode (table 5). 400ksps, +5v, 8-/4-channel, 12-bit adcs with +2.5v reference and parallel inter face 14 ______________________________________________________________________________________ table 2. control byte format table 4. channel selection for pseudo-differential operation (sgl/ dif = 0) table 3. channel selection for single-ended operation (sgl/ dif = 1) * channels ch4 ch7 apply to max1290 only. * channels ch4 ch7 apply to max1290 only. a1 ch0 0 + 0 - 0 a0 0 - 1 ch2 ch4* + 0 1 0 + - ch3 0 ch1 ch7* ch6* 1 ch5* 1 - + 0 0 0 a2 + - 1 0 1 - + 1 1 0 - 1 1 1 + 1 + - a1 ch0 0 + 0 0 a0 0 1 ch2 ch4* + 0 1 0 + ch3 - 0 ch1 ch7* - ch6* - com 1 ch5* 1 + - 0 0 0 a2 + 1 0 1 + 1 - - 1 0 1 1 1 + 1 - + - d6 d4 pd0 sgl/ dif acqmod a2 a0 a1 uni/ bip pd1 d5 d2 d0 (lsb) d1 d3 d7 (msb)
___________applications information power-on reset when power is first applied, internal power-on reset cir- cuitry activates the max1290/max1292 in external clock mode and sets int high. after the power supplies stabilize, the internal reset time is 10?, and no conver- sions should be attempted during this phase. when using the internal reference, 500? are required for v ref to stabilize. internal and external reference the max1290/max1292 can be used with an internal or external reference voltage. an external reference can be connected directly to ref or refadj. an internal buffer is designed to provide +2.5v at ref for both devices. the internally trimmed +1.22v refer- ence is buffered with a +2.05v/v gain. internal reference the full-scale range with the internal reference is +2.5v with unipolar inputs and ?.25v with bipolar inputs. the internal reference buffer allows for small adjustments (?00mv) in the reference voltage (figure 7). note: the reference buffer must be compensated with an external capacitor (4.7? min) connected between ref and gnd to reduce reference noise and switching spikes from the adc. to further minimize reference noise, connect a 0.01? capacitor between refadj and gnd. external reference with the max1290/max1292, an external reference can be placed at either the input (refadj) or the output (ref) of the internal reference-buffer amplifier. using the refadj input makes buffering the external reference unnecessary. the refadj input impedance is typically 17k ? . when applying an external reference to ref, disable the internal reference buffer by connecting refadj to v dd . the dc input resistance at ref is 25k ? . therefore, an external reference at ref must deliver up to 200? dc load current during a conversion and have an output impedance less than 10 ? . if the refer- ence has higher output impedance or is noisy, bypass it close to the ref pin with a 4.7? capacitor. power-down modes to save power, place the converter in a low-current shutdown state between conversions. select standby mode or shutdown mode using bits d6 and d7 of the control byte (tables 1 and 2). in both software power- down modes, the parallel interface remains active, but the adc does not convert. standby mode while in standby mode, the supply current is 1ma (typ). the part powers up on the next rising edge on wr and is ready to perform conversions. this quick turn-on time allows the user to realize significantly reduced power consumption for conversion rates below 400ksps. shutdown mode shutdown mode turns off all chip functions that draw quiescent current, reducing the typical supply current to 2? immediately after the current conversion is com- pleted. a rising edge on wr causes the max1290/ max1292 to exit shutdown mode and return to normal operation. to achieve full 12-bit accuracy with a 4.7? reference bypass capacitor, 500? is required after power-up. waiting 500? in standby mode, instead of in full-power mode, can reduce power consumption by a factor of 3 or more. when using an external reference, max1290/max1292 400ksps, +5v, 8-/4-channel, 12-bit adcs with +2.5v reference and parallel inter face ______________________________________________________________________________________ 15 table 5. data-bus output (8 + 4 parallel interface) v dd = +5v 330k ? 50k ? gnd 50k ? 0.01 f 4.7 f refadj ref max1290 max1292 figure 7. reference voltage adjustment with external potentiometer pin hben = 0 hben = 1 d0 bit 0 (lsb) bit 8 d1 bit 1 bit 9 d2 bit 2 bit 10 d3 bit 3 bit 11 (msb) bipolar (uni/ bip = 0) unipolar (uni/ bip = 1) d4 bit 4 bit 11 0 d5 bit 5 bit 11 0 d6 bit 6 bit 11 0 d7 bit 7 bit 11 0
max1290/max1292 only 50? is required after power-up. enter standby mode by per forming a dummy conversion with the con- trol byte specifying standby mode. note: bypass capacitors larger than 4.7? between ref and gnd result in longer power-up delays. transfer function table 6 shows the full-scale voltage ranges for unipolar and bipolar modes. figure 8 depicts the nominal, unipolar input/output (i/o) transfer function, and figure 9 shows the bipolar i/o transfer function. code transitions occur halfway between successive-integer lsb values. output coding is binary, with 1 lsb = (v ref / 4096). maximum sampling rate/ achieving 475ksps when running at the maximum clock frequency of 7.6mhz, the specified 400ksps throughput is achieved by completing a conversion every 19 clock cycles: 1 write cycle, 3 acquisition cycles, 13 conversion cycles, and 2 read cycles. this assumes that the results of the last conversion are read before the next control byte is written. it? possible to achieve higher throughputs (figure 10), up to 475ksps, by first writing a control word to begin the acquisition cycle of the next conver- sion, then reading the results of the previous conver- sion from the bus. this technique allows a conversion to be completed every 16 clock cycles. note that switching the data bus during acquisition or conversion can cause additional supply noise that can make it diffi- cult to achieve true 12-bit performance. layout, grounding, and bypassing for best performance, use pc boards. wire-wrap config- urations are not recommended since the layout should ensure proper separation of analog and digital traces. do not run analog and digital lines parallel to each other, and do not lay out digital signal paths underneath the adc package. use separate analog and digital pc board ground sections with only one star point (figure 11) con- necting the two ground systems (analog and digital). for lowest noise operation, ensure the ground return to the star ground? power supply is low impedance and as short as possible. route digital signals far away from sen- sitive analog and reference inputs. 400ksps, +5v, 8-/4-channel, 12-bit adcs with +2.5v reference and parallel inter face 16 ______________________________________________________________________________________ 111 . . . 111 111 . . . 110 100 . . . 010 100 . . . 001 100 . . . 000 011 . . . 111 011 . . . 110 011 . . . 101 000 . . . 001 000 . . . 000 1 02 input voltage (lsb) output code zs = com fs = ref + com fs 2048 (com) 1 lsb = ref 4096 fs - 3 / 2 lbs full-scale transition figure 8. unipolar transfer function 011 . . . 111 011 . . . 110 000 . . . 010 000 . . . 001 000 . . . 000 111 . . . 111 111 . . . 110 111 . . . 101 100 . . . 001 100 . . . 000 - fs com* input voltage (lsb) output code zs = com +fs - 1 lsb *com v ref / 2 + com fs = ref 2 -fs = + com -ref 2 1 lsb = ref 4096 figure 9. bipolar transfer function table 6. full scale and zero scale for unipolar and bipolar operation unipolar mode bipolar mode com com zero scale zero scale -v ref /2 + com negative full scale v ref + com v ref /2 + com positive full scale full scale
high-frequency noise in the power supply (v dd ) could influence the proper operation of the adc? fast com- parator. bypass v dd to the star ground with a network of two parallel capacitors, 0.1? and 4.7?, located as close as possible to the max1290/max1292 power- supply pin. minimize capacitor lead length for best sup- ply-noise rejection, and add an attenuation resistor (5 ? ) if the power supply is extremely noisy. __________________________definitions integral nonlinearity integral nonlinearity (inl) is the deviation of the values on an actual transfer function from a straight line. this straight line can be either a best-straight-line fit or a line drawn between the endpoints of the transfer function, once offset and gain errors have been nullified. the max1290/max1292? inl is measured using the end- point method. differential nonlinearity differential nonlinearity (dnl) is the difference between an actual step width and the ideal value of 1 lsb. a dnl error specification of less than 1 lsb guarantees no missing codes and a monotonic transfer function. aperture jitter aperture jitter (t aj ) is the sample-to-sample variation in the time between the samples. aperture delay aperture delay (t ad ) is the time between the rising edge of the sampling clock and the instant when an actual sample is taken. max1290/max1292 400ksps, +5v, 8-/4-channel, 12-bit adcs with +2.5v reference and parallel inter face ______________________________________________________________________________________ 17 clk acquisition control byte conversion low byte high byte d7 d0 d11 d8 low byte high byte d7 d0 d11 d8 acquisition sampling instant 123 4 5 6 78 910111213141516 wr rd hben d7 d0 state control byte figure 10. timing diagram for fastest conversion
max1290/max1292 signal-to-noise ratio for a waveform perfectly reconstructed from digital samples, signal-to-noise ratio (snr) is the ratio of the full-scale analog input (rms value) to the rms quanti- zation error (residual error). the ideal, theoretical mini- mum analog-to-digital noise is caused by quantization error only and results directly from the adc? resolution (n bits): snr = (6.02 ? n + 1.76)db in reality, there are other noise sources besides quanti- zation noise, including thermal noise, reference noise, clock jitter, etc. therefore, snr is computed by taking the ratio of the rms signal to the rms noise, which includes all spectral components minus the fundamen- tal, the first five harmonics, and the dc offset. signal-to-noise plus distortion signal-to-noise plus distortion (sinad) is the ratio of the fundamental input frequency? rms amplitude to the rms equivalent of all other adc output signals. sinad (db) = 20 ? log (signal rms / noise rms ) effective number of bits effective number of bits (enob) indicates the global accuracy of an adc at a specific input frequency and sampling rate. an ideal adc? error consists of quanti- zation noise only. with an input range equal to the adc? full-scale range, calculate the enob as follows: enob = (sinad - 1.76) / 6.02 total harmonic distortion total harmonic distortion (thd) is the ratio of the rms sum of the input signal? first five harmonics to the fun- damental itself. this is expressed as: where v 1 is the fundamental amplitude, and v 2 through v 5 are the amplitudes of the 2nd- through 5th-order harmonics. spurious-free dynamic range spurious-free dynamic range (sfdr) is the ratio of the rms amplitude of the fundamental (maximum signal component) to the rms value of the next-largest distor- tion component. thd vvvv v log / = +++ ? ? ? ? ? ? ? ? ? ? 20 2 2 3 2 4 2 5 2 1 400ksps, +5v, 8-/4-channel, 12-bit adcs with +2.5v reference and parallel inter face 18 ______________________________________________________________________________________ 3v/5v v logic = 3v/5v gnd supplies dgnd 3v/5v gnd 4.7 f 0.1 f v dd digital circuitry max1036 max1037 max1038 max1039 r* = 5 ? *optional figure 11. power-supply and grounding connections chip information transistor count: 5781 substrate connected to gnd
max1290/max1292 400ksps, +5v, 8-/4-channel, 12-bit adcs with +2.5v reference and parallel inter face ______________________________________________________________________________________ 19 typical operating circuits v dd ref refadj ch6 ch5 ch4 ch3 ch2 ch1 ch0 com gnd 4.7 f 0.1 f +5v +2.7v to +5.5v +2.5v output status p control inputs clk cs wr rd d7 d6 d5 d4 d3/d11 d2/d10 d1/d9 d0/d8 p data bus ch7 int hben p control inputs analog inputs v logic max1290 v dd ref refadj ch3 ch2 ch1 ch0 com gnd gnd gnd 4.7 f 0.1 f +5v +2.7v to +5.5v +2.5v output status clk cs wr rd d7 d6 d5 d4 d3/d11 d2/d10 d1/d9 d0/d8 p data bus int hben analog inputs v logic max1292 pin configurations (continued) ordering information (continued) part temp range pin-package inl (lsb) max1292beeg max1292aeeg -40? to +85? ? -40? to +85? 0.5 24 qsop 24 qsop MAX1292BCEG max1292 aceg 0? to +70? ? 0? to +70? 0.5 24 qsop 24 qsop 28 27 26 25 24 23 22 21 20 19 18 17 16 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 v logic v dd ref refadj gnd com ch7 ch0 ch1 ch2 ch3 ch4 ch5 ch6 cs clk wr rd int d0/d8 d1/d9 d2/d10 d3/d11 d4 d5 d6 d7 hben qsop top view max1290
max1290/max1292 400ksps, +5v, 8-/4-channel, 12-bit adcs with +2.5v reference and parallel inter face maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circuit patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. 20 ____________________maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 2002 maxim integrated products printed usa is a registered trademark of maxim integrated products. qsop.eps package information (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation go to www.maxim-ic.com/packages .)

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